PEX 8649
48-Lane, 12-Port PCI Express Gen 2 (5.0 GT/s) Switch, 27 x 27mm FCBGA
The ExpressLane™ PEX 8649 device offers 48 PCI Express Gen 2 (5.0 GT/s) lanes, capable of configuring up to 12 flexible ports. The switch conforms to the PCI Express Base Specification, rev 2.0. The 48-lane switch enables users to add scalable, high bandwidth, non-blocking interconnection to a wide variety of applications including servers, communications, storage, blade servers, and embedded systems. The PEX 8649 supports the PCI-SIG defined Multicast protocol for PCI Express. The PEX 8649 also features Multi-root architecture with up to four upstream ports as well as an on-chip Non-Transparent port for dual-host and failover applications, as well as three on-chip Hot-Plug controllers, allowing users to implement single-chip solutions. The device is hardware configurable and software programmable, allowing users to tailor their port configurations and QoS operating characteristics to suit their application requirements. The PEX 8649 is offered in a 27 x 27mm 676-ball FCBGA. This device is available in lead-free packaging. This device supports Access Control Services (ACS).
Page Index
Related Gen 1 Devices
Related Gen 2 Devices
Supporting Documentation
- PCIe Technical Info & White Papers
- General PLX Product Documentation
- Support Documentation (Quality, FAQs, RoHS...)
Hot Applications
Usage Models
Suitable for multi-host systems, communications and storage
PEX 8649 Technical Documentation
| Document/Resources | Everyone Access | Requires Membership | Requires NDA | Description | Version | Date |
|---|---|---|---|---|---|---|
| Product Brief | Download | Product Overview | 1.1 | 05/09 | ||
| Data Book | Download | Detailed Technical Specifications | 1.2 | 01/10 | ||
| Design Notes | Download | Power Management Modes, PEX 8600 Products (white paper) | 1.0 | 04/08 | ||
| Download | Read Pacing, 8600 family feature (white paper) | 1.0 | 10/07 | |||
| Download | Dynamic Buffer Pool, 8600 family feature (white paper) | 1.0 | 10/07 | |||
| Download | Error Recovery and Fencing Mechanisms (white paper) | 1.0 | 01/08 | |||
| Download | Non-Transparent Mode: Setup & Demonstration (white paper) | 1.0 | 04/09 | |||
| Download | Schematic Design Checklist | 1.0 | 07/09 | |||
| Download | Quick Start Hardware Design Guide | 0.1 | 07/09 | |||
| Errata | Download | Silicon Revisions and Errata List | 0.5 | 12/09 | ||
| Interoperability | Download | Interoperability Test Report | 1.0 | 10/09 | ||
| Application Notes | Download | Gen 2 switch compatibility with Gen 1 devices | 1.2 | 11/09 | ||
| Download | Non-Transparent (NT) Bridging using PEX 8649 | 1.0 | 12/09 | |||
| Migration Document | Download | PEX 8649 Pin Compatibility with PEX 8648 | 2.0 | 04/09 | ||
| Part Numbers Listing | View HTML | Part Number, Listing and Compliance | -- | -- | ||
| Quality & Reliability | Download | Moisture/Reflow Sensitivity Classification (IPC/JEDEC J-STD-020D.1) | -- | 03/08 | ||
| Download | RoHS 6/6 Certificate of Compliance (PEX8000 ending with the suffix F or G) | -- | -- | |||
| Download | ICP Test Report | -- | -- | |||
| Download | RoHS Certificate of Compliance (FCBGA) | -- | -- | |||
| Download | Reliability Qualification Report | 2.2 | 11/09 | |||
| Download | Lead-Free Material Analysis Data (27x27mm) | -- | -- | |||
| Download | RoHS Certificate of Compliance (PBGA) | -- | 01/10 | |||
| Download | RoHS 6/6 Certificate of Compliance (PEX86xx Flip Chip BGA products with a suffix \'F\') | -- | -- |
PEX 8649 Development Tools
| Document/Resources | Everyone Access | Requires Membership | Requires NDA | Description | Version | Date |
|---|---|---|---|---|---|---|
| Signal Integrity Kit | Download | PLX Gen 2 Testing over "16 / 30" Tyco Comm Backplane (presentation) | 1.0 | 12/08 | ||
| Download | PCIe Receiver Equalization (white paper) | 1.0 | 12/08 | |||
| Download | Using PEX 8648 SMA based (SI) Card (white paper) | 1.0 | 12/08 | |||
| Download | PLX PCI Express over 30" of Legacy Backplane (white paper) | 1.0 | 07/08 | |||
| Download | Tool provides loss estimation and bandwidth distortion for a specified trace distance and configuration. | 2.0 | 06/08 | |||
| Rapid Development Kit (RDK) | Download | Hardware Reference Manual | 1.0 | 12/09 | ||
| Software Development Kit (SDK) | View HTML | Software Development Kit | -- | -- | ||
| BSDL | Download | Boundary Scan Description Language files | 1.1 | 10/09 | ||
| HSPICE Model | Download | HSPICE Model | 1.0 | 04/09 | ||
| OrCAD | Download | OrCAD Library | -- | -- | ||
| Download | Pinout List | 1.0 | 11/09 |
PEX 8649 Applications
| Application | Description | Document | |
|---|---|---|---|
| Backplane Application in Embedded Systems |
High Lane/Port Count Fan-Out | ExpressApps #74 (PDF) |
|
| Using Multicast in PCIe systems | Multicast, and up to 5 upstream ports, provide efficient CPU utilization and failover | ExpressApps #71 (PDF) |
|