PCI Express News

September 2007

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In this issue:

PCI Express

PCI Express Gen 2 Switch Family Announced

IOV logoThe new ExpressLane? PCIe Gen 2 switches include the PEX 8648 (48 lanes, 12 ports), PEX 8632 (32 lanes, 12 ports), PEX 8624 (24 lanes, 6 ports), PEX 8616 (16 lanes, 4 ports) and PEX 8612 (12 lanes, 3 ports). These Gen 2 switches share a field-tested and proven PLX architecture with industry-leading features including the lowest latency and power, highest performance, integrated non-transparent ports and Hot-Plug controllers, the smallest Flip-Chip packaging, and highly flexible port configurations up to x16 -- all elements that feed the requirements of next-generation graphics, backplanes, server, storage, HBA/NIC, and embedded markets.

PLX's PCI Express Gen 2 switches are fully compliant with the PCI-SIG™ PCIe Base Specification r2.0, which doubles the interconnect bit rate over its predecessor to 5 GT/s (GigaTransfers per second) from 2.5 GT/s, and are backward compatible with PCIe Base Specification r1.0/1.0a/1.1 (PCIe Gen 1), allowing ease of migration for existing designs. PLX's Gen 2 switches integrated Non-Transparent Port allows for a single-chip solution in dual-host, failover, and redundant systems, as well as intelligent I/O modules. Unique power-reduction methods and a proprietary Cut-Thru design for low latency down to 140ns are achieved through the company's signature engineering features achieved with PLX's third-generation PCIe architecture. A new technical white paper discussing the important role of low-latency components in designing high-performance PCIe systems can be found on the PLX Website at www.plxtech.com/techinfo.

PLX's new switches complement 5GT/s speed with patent pending exclusive features such as Read Pacing, Dual Cast and Dynamic Credit Allocation to improve system performance. The Dual Cast feature allows for the copying of data (e.g. packets) from one ingress port to two egress ports allowing for higher performance in dual-graphics, storage, security, and redundant applications. By offloading the task of backing up data onto the secondary system/device, processor and system performance is enhanced. A typical application (see graphic) of Dual Cast is Fibre Channel host-bus adapter (HBA) storage: Whereas the PLX switch uses Dual Cast to simultaneously store data on two RAID controllers, the same card can be used for non-redundant applications.

Read Pacing allows desired distribution of system bandwidth in host-centric applications, providing greater throughput in data transfers from host memory. The Read Pacing feature allows users to throttle the amount of read requests being made by downstream devices. When a downstream device requests several long reads back-to-back, the Root Complex gets tied up in serving this downstream port. If this port has a narrow link and is therefore slow in receiving these read packets from the Root Complex, then other downstream ports may become starved ? thus, impacting performance. The Read Pacing feature enhances performances by allowing for the adequate servicing of all downstream devices.

PLX housed its Gen 2 switches in the market's smallest footprint Flip-Chip packaging (19x19mm) to provide superior signal integrity while designing the ball placement for easy board layout. Additional PLX advantages include several on-chip debug features, error-injection support, and performance monitoring counters to name a few. All of these features are extremely valuable for system-level validation and bring-up. PLX Gen 2 switches are also unique in that they do not have power sequencing requirements and they need only two power supplies.

Press release link
Datasheets/Support: www.plxtech.com/gen2

PLX Gen 2 Switches are Backward Compatible to 1.0/1.0a/1.1

PLX's Gen 2 switches (PEX 8600 product family) are backwards compatible with PCIe Gen 1 devices. The PEX 8600 switches enable a PCIe Gen 2 (5.0Gbps) native chipset to create PCIe Gen 1 (2.5Gbps) slots and/or communicate with PCIe Gen1 endpoints. The PEX 8600 switches will automatically negotiate down to Gen 1 bit-rates (2.5Gpbs) when connected to a Gen 1 endpoint. Conversely, the PEX 8600 switches can be used to create Gen 2 slots and/or communicate with Gen 2 endpoints on a Gen 1 native chipset.

Customers having compatibility issues between PCIe Gen 2 and PCIe Gen 1 can now design-in PLX's PEX 8600 switches to resolve their compatibility problems.

Datasheets/Support: www.plxtech.com/gen2

Unique Key Features of Gen 2 Switches Help Validate Systems

Additional key features designed into the new PLX Gen 2 chips include extensive debug features which will be especially valuable for customers when validating Gen 2 at the systems level. For example:

Debug and Monitoring Features

  • Access to parallel data inside the device
  • PRBS generator for bit error rate characterization
  • SerDes loopback mode
  • Error Injection
  • Error counters
  • DLLP/TLLP counters

Datasheets are ready on the PLX Website for current customers under NDA, or register to apply for access.

Industry's Smallest Packaging Released

Dubbed Altair-Mini, PLX has now made available 48 lane, 32 lane, and 24 lane PCIe Gen 1 switches in the industry's smallest packages. PEX 8548S (48 lanes, 9 ports, 27x27mm), PEX 8547S (48 lanes, 3 ports, 27x27mm), PEX 8533S (32 lanes, 6 ports, 23x23mm), and PEX 8525S (24 lanes, 5 ports, 23x23mm) also offer the lowest latency and lowest power down to 110ns and 2.6W typical respectively.

Smaller packaging means less board space for design engineers, and that comes at a premium in today's shrinking applications. PLX offers the smallest packaging and highest performance parts in its best-in-class product portfolio. PLX maintains the smallest Gen 1 and Gen 2 switches on the market.

Datasheets and other support can be found on www.plxtech.com/pcie

PLX Leads in all Performance and Physical Parameters

PLX recently ran some in-depth comparison tests against the competition and found its chips to be superior in all aspects ranging from lower power to faster throughput to smaller package size. The following is a synopsis of these results.

  • Performance per watt: PLX is up to 35% better.
    - Performance matters when high throughput is needed.
  • Latency: Competition shows up to 87% higher latency. Lower latency is of course better!
    - Latency counts when quick read/write response is desired.
  • Power consumption: Competition shows up to 46% higher power consumption.
    - Minimizing power consumption is the key to reducing system heat and energy costs.
  • Package size: Competition offers up to 47% larger packaging. Smaller is better!
    - Smaller packaging reduces cost and makes layout more efficient.
  • Single-chip solutions: Competition offers no integrated Dual-Host, Failover or Hot-plug, thus extra devices are often needed. Less BOM is better!
    - Single chip solutions from PLX are critical for bill of material cost and board space optimization.
  • Port Flexibility: Competition offers only fixed upstream ports. No flexibility!
    - Flexibility is important for ease of design & re-use. PLX has moveable upstream ports and any port can be upstream.

Get the details by contacting a PLX technical sales representative.

PCI-SIG Announces PCI Express 3.0 Bit Rate

PCI-SIG™, the Special Interest Group responsible for PCI Express™ industry-standard I/O technology, has announced the approval of 8GT/s as the bit rate for the next generation of PCIe™ architecture, PCIe r3.0. The 8GT/s bit rate represents a doubling of the delivered bandwidth by removing the requirement for the 8b/10b encoding scheme supported in prior versions of PCIe architecture, which imposed a 20 percent overhead on the raw bit rate. Removal of the 8b/10b encoding scheme will effectively provide the same bandwidth (2x Gen 2) as a 10G interface would with 8b/10b encoding.

The PCIe r3.0 specification will introduce a number of optimizations for enhanced signaling and data integrity, including transmitter and receiver equalization, PLL improvements, clock data recovery, and channel enhancements for currently supported topologies.

PLX has been working closely with the PCI-SIG and the company expects to have enhanced silicon shortly after the final base specification is released.

Read the full article on the PCI-SIG Website www.pcisig.com

Designing for Low Latency in PCIe Systems

Overcoming PCI Express latency isn't simply a matter of choosing the lowest-latency components from among those suitable for an embedded-system design, but it's a good place to start. It's also a matter of architecting operations to reduce or eliminate the sensitivity of system performance to latency. It's impossible to mask all the latency, so the less there is to begin with, the better.

Latency is the delay between starting and completing an action. For a switch, it's the time between the start-of-packet (SoP) symbol on an input pin and the SoP symbol on an output pin for the same packet forwarded through the switch. From an endpoint's perspective, the latency includes the packet transmission time, since it can't use the data until it has seen the cyclic redundancy check (CRC) at the end and checked for errors. At the highest level, the overall task latency, which may include multiple switch latencies, is what really matters. At issue is whether resources are idled during the waiting period implied by a task or transfer latency, and whether the waiting time prevents a deadline from being met.

Read the full article in embedded.com magazine

PCI Express Hot-Plug: A New Era of RAS

Server reliability, availability and serviceability (RAS) have become crucial for businesses, and as RAS approaches a guaranteed up-time availability target of 99.999 percent, or "five nines," the importance of replacing or adding components on the fly has become critical. PCI Express (PCIe) was introduced into the PC and server environments as a serial communications interface standard and since then has built such traction that it's now the protocol of choice in the server interconnect arena. The need for PCIe slots on these servers to be hot-plug ready has become extremely important, as is evident in next-generation designs. Hot-plug functionality is essential to maintaining "highly available" server systems.

The fundamental purpose of hot-plug functionality is to allow the orderly live insertion and extraction of boards or enclosures without adversely effecting system operations. This is typically done to repair or replace faulty devices, as it is often difficult, if not impossible, to schedule downtime on a server to replace or install peripheral cards. The ability to insert or replace I/O devices this way eliminates or at least minimizes system downtime. This technique can also be used to add new functionality for the reconfiguration of the systems. Laptop users also need hot-plug capability to swap cards that provide I/O functions, such as disk drives and communications ports built into docking stations.

Read the full article in EEPN magazine

PCI Express 2.0: The Next Frontier in Interconnect Technology

The widespread success of PCI Express continues with the rollout of the 2.0 specification. The spec brings with it wider bandwidth for users and tighter design conditions for developers. PCIe is now the de facto standard for I/O in the server and PC interconnect arena. The PCI Special Interest Group (PCI-SIG) has recently released the updated PCIe 2.0 Base Specification, which offers significant enhancements over its predecessor, PCIe 1.1, at the physical, access control, software notification and system levels. This was accomplished while maintaining full backward compatibility with PCIe 1.1 hardware and software.

PCIe 2.0 doubles PCIe 1.1's rated speed, to 5 GigaTransfers per second (GT/s), effectively increasing the aggregate bandwidth of a 16-lane link to approximately 16 Gbyte/s. GigaTransfers are used to measure PCIe 2.0 bandwidth because PCIe uses 8b/10b encoding, whereby every eight bits are encoded into a 10-bit symbol.

Read the full article in RTC magazine

PLX Products at a Glance - New Snapshot Flyer

This simplified one page flyer lists all PLX products and their main attributes. The PDF shows all released Gen 1 and Gen 2 Switch and Bridge products on one easy reference page, as well as all PCI, I/O Accelerators and USB controllers on the backside. Access here

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