PCI Express Gen 2 Switch Family Available Now
The PLX ExpressLane PCIe Gen 2 switch family includes the PEX 8648 (48 lanes, 12 ports), PEX 8632 (32 lanes, 12 ports), PEX 8624 (24 lanes, 6 ports), PEX 8616 (16 lanes, 4 ports) and PEX 8612 (12 lanes, 3 ports) devices, with more Gen 2 products already in development. Cutting-edge, PLX only, integrated on-chip features for enhancing performance include Read Pacing, Dual Cast, Dynamic Buffer Allocation, as well as non-transparency, port flexibility, Hot-Plug circuitry and special embedded diagnostic tools that customers can use to help bring their own systems to market faster.
Industry-leading new features are achieved through a unique package of PLX Gen 2 engineering solutions that greatly enhance system performance and widen the gap compared to other solutions. This includes Read Pacing (increases performance by removing system bottlenecks), Dual Cast (enhances performance by simultaneously sending data from one port to two ports), and Dynamic Buffer Allocation (allows increased throughput by absorbing dynamic increments in bandwidth requirements).
| Part Number |
Lanes |
Ports |
Read Pacing |
Dual Cast |
Dynamic Buffer Allocation |
Hot-Plug Controllers |
Non-
Transparency |
Latency (ns) |
Package Size (mm) |
Power (W) Typ. |
Availability |
| PEX 8648 |
48 |
12 |
Yes |
Yes |
Yes |
Yes |
Yes |
140 |
27 x 27 |
4.0 |
Now |
| PEX 8632 |
32 |
12 |
Yes |
Yes |
Yes |
Yes |
Yes |
145 |
27 x 27 |
2.8 |
Now |
| PEX 8624 |
24 |
6 |
Yes |
Yes |
Yes |
Yes |
Yes |
145 |
19 x 19 |
3.0 |
Now |
| PEX 8616 |
16 |
4 |
Yes |
Yes |
Yes |
Yes |
Yes |
150 |
19 x 19 |
2.2 |
Now |
| PEX 8612 |
12 |
3 |
Yes |
Yes |
Yes |
Yes |
Yes |
150 |
19 x 19 |
2.0 |
Now |
Datasheets: www.plxtech.com/gen2
Sales: www.plxtech.com/contact
Read Pacing Can Deliver >10x Improved Performance
 Fan-out is the most common use of PCIe switches. In the DMA I/O model prevalent in workstations and servers, DMA controllers in the I/O device endpoints both write blocks of data to host memory and read from it. The host connection is a point of aggregation that is usually wider than any of the endpoint connections without necessarily being as wide as the sum of the widths of all them. If not, then congestion and bandwidth sharing are primary concerns. Even in the ideal case of host bandwidth equaling or exceeding the sum of all the devices’ bandwidth, read completions are often delivered to an endpoint faster than it can consume them, leading to congestion and to the starvation of other endpoints. PLX has implemented the patent pending Read Pacing feature in its Gen 2 ExpressLane switch family (PEX 8600) to solve the problem.
Customers with NDA access to the PLX Website can download a whitepaper discussing Read Pacing here.
PLX is now touring the globe with a dynamic performance demonstrating Read Pacing. Customers can also attend a demonstration at the Embedded Systems Conference in San Jose April 14-18.
Dynamic Buffer Allocation Feature Delivers Higher Performance 
Available on-chip memory utilization and architecture are critical in determining the performance and throughput of a switch. When architecting a switch, one can choose between fixed and dynamic buffer memory allocation. PLX’s doubly bifurcatable port architecture (x16 to two x8 or four x4s) both provides highly flexible port configurations and lends itself to Dynamic Buffer Allocation (DBA). Dynamic Buffer Allocation makes best use of available switch memory, leading to higher performance and/or lower cost. PLX has implemented the Dynamic Buffer Allocation feature in its Gen 2 ExpressLane switch family (PEX 8600).
Customers with NDA access to the PLX Website can download a whitepaper discussing DBA here.
Powerful 5.2 SDK Upgrade Delivers New Tools
The PLX Technology Software Development Kit, or SDK, is a highly customized software package containing powerful tools to help customers get to market faster when designing in PLX PCI Express devices. The new 5.2 SDK application offers an easy to use enhanced user interface that includes a variety of new and useful tools especially helpful for PLX PCIe Gen 2 switch customers. This SDK is an integral part of the PLX Rapid Development Kit (RDK) which includes both hardware and software and is a key utility for engineers seeking efficiency and the highest possible performance.
Premium features of the new PLX SDK includes: PEX Device Editor (PDE) GUI Utility; Register Access, EEPROM Programming; Sample Command Line Applications; Performance Monitoring; SerDes Eye Width Diagram; Exerciser Mode; Probe Mode; Debug Diagnostics Utility; Easy access via I2C.
One powerful feature is the ability of in-system extraction of receive data “Eye Width” thru the SDK. This includes the ability to extract the width of the receiver eye inside the chip. Access is provided via the I2C connector to the PLX RDK board. This enables designer to make trade-offs on the SerDes settings. Other value-added features of the 5.2 SDK include the ability to create user-programmable PCIe packets generated by the device to enable high density traffic, an “Error Injection” utility, and completely passive performance monitoring.
There is an NDA requirement for using the PLX SDK with PCIe switch devices. During installation of the SDK, the installer will ask for a key. This key can be obtained from your local PLX sales representative. Customers can download the new SDK at www.plxtech.com/sdk
AMD's New Premium Dual GPU Graphics Cards Feature PLX Switch
 PLX PCIe SWITCH UNLEASHES MAXIMUM THROUGHPUT ON REVOLUTIONARY ATI RADEON™ HD 3870 X2 GRAPHICS CARDS
PLX’s PEX 8547 PCIe switch is being used for high-performance fanout in AMD’s (NYSE: AMD) innovative new high-end ATI Radeon™ HD 3870 X2 Dual-GPU graphics cards, now officially released and targeting extreme-gaming enthusiasts.
The PLX ExpressLane PEX 8547 PCIe switch was designed specifically for intense graphics applications like the ATI Radeon™ HD 3870 X2, and offers 48 lanes, three ports, remarkably low latency (only 110 nanoseconds), true peer-to-peer traffic, large packet memory (1024 byte maximum payload size) and a non-blocking internal switch architecture that provides a full line rate on all ports for performance-hungry graphics applications.
“AMD’s ground-breaking ATI Radeon™ HD 3870 X2 graphics cards, supported by PLX PEX 8547 PCIe switches, have demonstrated terrific performance in chart-topping computer games. AMD chose the PLX chip for its industry-leading PCIe features, allowing high-bandwidth peer-to-peer communication between its two powerful next generation Radeon graphics processors leveraging ATI CrossFireX™ technology on a single board,” said Matt Skynner, vice president of marketing, Graphics Products Group, AMD. “PLX has provided AMD with enhanced flexibility and performance in our designs. Their technical proficiency and top notch customer experience has been a great asset to help create the ATI Radeon HD 3870 X2 graphics cards.”
Read the press release
Over 2 Million PLX PCIe Chips Now Shipped
PLX has been leading the global adoption of PCI Express into exceedingly broader markets, and is now announcing it has shipped over two million PCIe switch and bridge chips to customers. This significant milestone shows how PCIe has increasingly replaced legacy PCI designs and alternate interconnect solutions with its rapid growth year-over-year. PLX is by far the industry leader by a large margin with more than 60% market share due to the company’s early and ongoing commitment to the standard.
The widening acceptance of PCIe now fully engulfs Servers, Storage, PC Peripherals, Embedded, and Communications applications. Interest from customers in PCIe Gen 2 switching is very encouraging, and we anticipate ongoing strong growth in new designs across all segments.
Datasheets/Support: www.plxtech.com/pcie
Contact Sales: www.plxtech.com/contact
Using PLX Gen 2 Switches in Gen 1 Systems is a No Brainer
PLX recommends that customers design-in Gen 2 switches today, even if Gen 1 platforms are being used, and stay ahead of the performance game. This allows designers to take advantage of PLX’s new premium Gen 2 features including Read Pacing, Dual Cast, DBA, lower power, smaller footprint and a lower cost. When your designs or endpoints ramp to Gen 2, you will be ready and performance rich! 
PLX Gen 2 PEX 8600 switches can be used in any Gen 1 system. The switches will automatically operate in Gen 1 mode if placed in a Gen 1 system. Conversely, the Gen 2 PEX 8600 switches can be used to create Gen 2 slots and/or communicate with Gen 2 endpoints on a Gen 1 native chipset. PLX Gen 2 switches can also be used in any mixed Gen 1/Gen 2 system because the switch ports automatically adjust depending on the attached device. The switch will respond as a bridge from Gen 2 to Gen 1 and vice versa.
Important! Gen 2 costs today are lower than Gen 1 costs, meaning customers can benefit not only financially, but reap the benefits of the most sophisticated PCIe switches and support tools on the planet! It’s a no brainer!
Datasheets/Support: www.plxtech.com/gen2
Contact Sales: www.plxtech.com/contact
Free PCIe 2.0 Technical Seminar, San Jose Registration Open
This technical presentation and demonstration covers the PCI Express 2.0 specification and some major building blocks required of PCIe systems including PCIe switches in actual usage models. Featured speaker is Mindshare, a well-known technical training specialist firm, along with PLX Technology and will be hosted by global technical distribution experts, Avnet.
The “all day” classes will be held over two separate days to accommodate busy schedules. Register today before classes fill up. This special event will be hosted on the Avnet campus in San Jose, California (see map). Choose either Tuesday April 8th, or Wednesday April 9th 2008. Registration begins at 8am with classes beginning at 9am sharp and running until 4pm. Light Breakfast and Lunch provided.
Register here to reserve your seat: www.plxtech.com/pcie2seminar  
EDN lists PEX 8600 family for 2008 Annual Innovation Award
Editors at EDN, one of the most distinguished technology magazines in publication, selected the PEX 8600 family as finalist for their 2008 Annual Innovation Award. EDN chose the new PLX Gen 2 family based on the switches' array of powerful features, including 5GT/s throughput, flexibility of lane and port configurations, and functionality in a wide range of next-generation applications. Vote here for PLX to win!
EDN also cited several PLX technological breakthroughs in the PEX 8600 family: Read Pacing, which allows fair distribution of system bandwidth; Dynamic Buffering, a feature that optimizes the use of available PCIe switch memory; and Dual Cast, which enables data to be written simultaneously to two separate targets. (See article)
This is the second consecutive year PLX PCIe switches have achieved finalist status in the EDN Innovation Awards, which honor outstanding engineering professionals and products. In addition to being a finalist in this year’s awards program, the PEX 8600 family also was named one of EDN’s “Hot 100” products for 2007. (See article)
Reining in PCIe-based Embedded Systems' Latency – ESC Presentation
Join PLX’s Chief Systems Architect, Shreyas Shah, at the Embedded Systems Conference in San Jose on April 18th, 8:30am-10am for a technical presentation discussing the many ominous issues tied to latency with practical solutions.
Key Takeaways
An understanding of packet latency, the pitfalls of it remaining unchecked, and when and how to design with low-latency PCI Express switches.
Audience level: Advanced
Prerequisites
Understanding of various interconnect technologies in use today, including PCI Express; understanding of/experience in systems-level design with those technologies.
Presentation Abstract
While the PCI Express interconnect standard – both the original PCIe 1.x and the newer PCIe 2.0 (Gen 2) – permeates embedded-systems hardware, packet latency continues to impact systems’ overall performance. Latency is the delay between the start and completion of a system's action, and its greatest impact is in its affect on higher-level functional throughput. When a data packet is forwarded through a PCIe switch, for example, throughput is assumed to be at optimum speeds. This isn't guaranteed, however, because switch latency varies. But system designers don’t have to resign themselves to latency running amok. This class looks critically and deeply at PCIe packet latency, and provides attendees a greater understanding of how to contend with this issue.
Register for Embedded Systems Conference
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Access PCI Express datasheets, or update your PLX profile and newsletter subscriptions by logging in at http://www.plxtech.com/mydata/.
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